PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells during a configuration event that defines how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Due to their high degree of configurability, FPGAs are ideally suited for the implementation of one or more I/O interfaces that are capable of supporting a large number of input/output (I/O) interface standards. For example, many modern processing systems operate according to the peripheral component interconnect (PCI) standard, which among other features, defines a specification for attaching peripheral devices to a computer mother board. In other examples, modern processing systems may also utilize the high speed transceiver logic (HSTL) standard for data transfers to and from memory, and/or the low-voltage differential signaling (LVDS) standard for backplane communications.
Some of the I/O standards that may be supported by an FPGA also require a controlled impedance at the respective input and output terminals of the I/O buffers, so as to maintain signal integrity despite the increasingly faster edge rates that must be supported by the I/O buffer. Discrete resistors have traditionally been employed to provide such a controlled impedance, but the amount of circuit board area required by the discrete resistors is prohibitive, especially in light of the fact that modern FPGAs contain many banks of I/O buffers. In addition, locating each resistor in close proximity to each I/O buffer, as required to optimize impedance control, may be physically impossible.
Digitally controlled impedance (DCI) may, therefore, be employed to configure the I/O buffer with on-die termination impedance, thus obviating the need for external resistors. The DCI controller adjusts the output impedance, or the input termination impedance, to appropriately match the characteristic impedance of the transmission medium. In particular, a DCI controller is implemented for each bank of I/O buffers, whereby the DCI controller adjusts the impedance of each I/O buffer within the bank of I/O buffers to be proportional to the impedance magnitude of external reference resistors that are connected to impedance reference pins of each I/O bank. As such, each I/O buffer exhibits the correct input/output impedance that may be required by the controlled impedance I/O standard that may be supported by the I/O buffer.
In order to test controlled impedance I/O standards for each I/O bank, traditional test methodologies require that a pair of discrete resistors be connected to the impedance reference pins of each I/O bank under test. Such resistor connections are typically implemented within special test equipment (STE) fixtures, whereby the STE fixtures facilitate the testing of multiple FPGAs simultaneously, by providing all I/O and power connections that are required for each test scenario.
Since each I/O bank of each FPGA is configurable, however, an I/O bank may be configured to support a controlled impedance I/O standard, such as HSTL, during a first test scenario, but may be re-configured to support a non-controlled impedance I/O standard, such as PCI, during a second test scenario. As such, the STE fixture is further required to employ switching means, such as relays, to connect the discrete resistors to the impedance reference pins of each I/O bank that is to be tested during the first test scenario. The STE fixture is then required to disconnect the discrete resistors from the impedance reference pins of each I/O bank that is to be tested during the second test scenario.
STE fixtures are often configured as multi-site testers, whereby multiple FPGAs are tested simultaneously. As such, the complexity of the STE fixture is necessarily exacerbated when the STE fixture is required to support the testing of both controlled and non-controlled impedance I/O standards for each I/O buffer of each FPGA under test. Efforts continue, therefore, to utilize the configurability of the FPGA to reduce the complexity of the STE fixture without sacrificing test support for controlled impedance I/O standards.